IC manufacturing technology is a complex process that advances rapidly. A key parameter to characterize the integrated circuit manufacturing technology is the minimum feature size, i.e., critical dimension (CD). Ongoing shrinkage of the critical dimension of circuit elements, even down to nanoscale width, has made it possible to integrate millions of devices on a chip.
Lithography is the driving force for the development of integrated circuit manufacturing technology, and is also one of the most sophisticated process. Lithography plays an important role in the integrated circuit manufacturing processes. Before starting a lithographic process, a pattern is transferred to a mask using a specific apparatus, and then the pattern of the mask is imaged onto a substrate (silicon wafer) using a specific wavelength of light through a lithographic apparatus to produce chips. However, due to the reduced size of semiconductor devices, distortion occurs in the transfer of mask pattern onto the wafer, and the distortion may cause failures of the manufacturing processes. Therefore, in order to solve the above problems, optical proximity correction (OPC) techniques are utilized to modify the mask to compensate for optical proximity effect of the exposure system.
In order to increase the contrast of the pattern in the OPC process, the target pattern (alternatively referred to as “main pattern” hereinafter) and scattering bar (alternatively referred to as “sbar” hereinafter) are generally formed on the mask. The scattering bar is disposed around the main pattern to generate optical proximity effects and are not formed on the wafer after exposure. The scattering bar may have various shapes such as long sham, block sham, etc. in general, conventional techniques use the middle portion of the image plane of a photoresist layer to collect data for the calibration of the OPC model of the main pattern, and simulate the sbar under an overexposure condition. However, due to the smaller size of sbar, light intensity of the sbar in the photoresist layer is much smaller than the light intensity of the main pattern, so that only the sbar is imaged onto the top surface of the photoresist layer, and the image plane of a conventional OPC template is imaged in the middle portion of the photoresist layer, so that it is not possible to accurately detect the sbar printing, and it is thus likely to have the sbar formed onto the wafer, resulting in device failure and low production yield.
Although the conventional method includes the simulation of the image plane of the main pattern and the sbar pattern and collection of data associated with the simulation, however, the simulation is only accurate in connection with the main pattern. Due to the small size of the sbar and the image plane on the top surface of the photoresist layer, the conventional method is not able to accurately simulate the sbar. Therefore, a need exists for an improved method to accurately simulate the sbar.